Flash and other types of electronic memory devices are constructed of memory cells operative to individually store and provide access to binary information or data. The memory cells are commonly organized into multiple cell units such as bytes which comprise eight cells, and words which may include sixteen or more such cells, usually configured in multiples of eight. Storage of data in such memory device architectures is performed by writing to a particular set of memory cells, sometimes referred to as programming the cells. Retrieval of data from the cells is accomplished in a read operation. In addition to programming and read operations, groups of cells in a memory device may be erased, wherein each cell in the group is programmed to a known state.
The individual cells are organized into individually addressable units or groups such as bytes or words, which are accessed for read, program, or erase operations through address decoding circuitry using wordlines and bitlines. Conventional flash memories are constructed in a cell structure wherein one or more bits of information or data are stored in each flash memory cell. In typical single bit memory architectures, each cell typically includes a MOS transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well.
The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
Other types of memory devices include ones comprising silicon or polysilicon above and below an ONO layer, these silicon-oxide-nitride-oxide-silicon devices are sometimes referred to as SONOS memory devices. Such devices may include physical dual bit memory cells, individually adapted to store two binary bits of data by localized charge trapping. The SONOS memory devices provide data retention with a thin bottom oxide, low-voltage operation, and fast programming speed.
Dual bit memory cells are generally symmetrical, including two identical and interchangeable source/drain regions. Application of appropriate voltages to the gate, drain, and source terminals allows access to one of the two bits (e.g., for read, program, erase, verify, or other operations). Core cells in flash memory devices, whether single bit or multiple-bit, may be interconnected in a variety of different configurations. For instance, cells may be configured in a virtual ground type configuration, with the control gates of the cells in a row individually connected to a wordline. In addition, the source/drain regions of memory cells in a particular column are connected together by a conductive bitline. In operation, individual flash cells and the individual data bits thereof, are addressed via the respective bitlines connected to first and second source/drain regions thereof and a wordline connected to the gate using peripheral decoder and control circuitry for programming (writing), reading, erasing, or other functions.
In most such array configurations the conductive wordlines and bitlines cross one another in accessing the individual flash cells, and therefore must be electrically isolated from one another by an insulative material layer. This wordline-bitline isolation layer may be formed similar to that of conventional LOCOS methods after deposition of the ONO layers and before the deposition of the conductive wordline.
As device densities increase and product dimensions decrease, it is desirable to reduce the size of individual memory cells including the features of the bitlines and wordlines associated with the cells, sometimes referred to as scaling. However, the fabrication techniques used to produce conventional dual-bit SONOS flash memory cells limit or inhibit the designer's ability to reduce cell dimensions. In a conventional manufacturing process whereby a bitline oxide may be formed, an ONO layer is formed on a substrate, over which a patterned resist is formed. An ONO etch is performed using the resist as a mask followed by an implantation to selectively introduce dopant impurities into portions of the substrate associated with prospective bitline regions thereof. The resist is then removed and one or more thermal oxidation processes is used to form a bitline oxide over the bitline and further drive the dopants deeper into the substrate.
Thereafter, a conductive wordline is formed over the ONO and prospective bitline oxide regions, for example, using polysilicon. In order to scale the memory cell devices to facilitate increased device densities, it is desirable to maintain a narrow bitline region without excess dopant diffusion yet obtain a thick bitline oxide layer for better bitline-wordline electrical isolation therebetween. However, limitations in the relatively high temperature and long duration furnace oxidation process used to form the bitline oxide, typically produce excessive bitline dopant diffusion and undesirable bird's beak areas underlying the ONO layer that effectively limit the ability to scale the device within desired performance specifications. Bitline oxides may be formed by current methods, but the thickness of such oxide layers formed over the nitride layer regions causes non-conformality in the oxide profile. Thus, there is a need for improved manufacturing techniques by which dual bit SONOS flash memory devices may be scaled without sacrificing device performance.